GPUs are evolving as massively threaded vector machines. While the primary design goal of the GPUs is efficient processing of the graphics stack, the massive parallelism available in these chips has lately opened up the possibility of carrying out general-purpose computing on them. This computing paradigm is called GPGPU. Although manually mapping regular data-parallel applications to GPUs has been explored quite extensively, making truly general-purpose computing feasible on GPUs requires answering a number of important questions. This half-day workshop aims at bringing together the researchers and practitioners in this rapidly evolving area with a goal of addressing issues related to programming languages, programming models, compiler optimizations, and architecture to make GPGPU a conducive execution environment for regular as well as irregular applications.

The topics of interest include, but are not limited to, the following.

• New GPU architecture features to enhance GPGPU
• Memory system innovations to enhance GPGPU
• Implications of GPGPU on memory consistency models
• Architecture support for single-chip CPU-GPU integration
• Programming models and language support for GPGPU
• Compiler Optimization for GPGPU
• Debugging/Performance visualization tools for GPGPU
• Efficient synchronization support for GPGPU
• Performance evaluation of irregular applications on GPUs
• Energy-efficiency studies on GPGPU
• GPGPU benchmarks

This half-day workshop will be held in conjunction with HPCA 2010 in Bangalore in January 2010.

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Registration is now open for the Workshop on Non-Traditional Programming Models for High-Performance Computing (part of The Los Alamos Computer Science Symposium). The symposium and workshop will be held in Santa Fe, New Mexico on October 13-14, 2009.

The goals of the workshop are two-fold:

1. To begin to identify, specify and capture in writing, the problematic issues and barriers inherent in today’s scientific software construction process.
2. To expose attendees to non-traditional programming models with the express purpose of igniting thought and discussion on the future of large-scale scientific programming.

The one-day workshop will consist of three sequential tracks, each lead by a moderator/facilitator. The tracks will include a small number of speakers who will each present a short position paper outlining their thoughts on current problems and how specific non-traditional techniques may be applied to address these issues. Following the presentations, the moderator will lead a discussion with the audience on the ideas presented by the speakers. Both the position papers and the captured discussion will be published on the workshop web site. It is the organizers’ hope that the output of this workshop, perhaps refined, can act as input to a future meeting or workshop on this topic.

This 3-day workshop, to be held  September 30, 2009 to October 2, 2009 in Lugano, Switzerland, will explore the use of GPUs, Cell BE processors FPGAs and special-purpose hardware for large-scale scientific computing.

Similar to the 1990s, when the revolution in mainstream scientific software development, viz. going from structured programming to object-oriented programming, was the greatest change in the past 3 decades, we are at the beginning of a totally new revolution in terms of algorithmic engineering.

We are nowadays at a hardware/software technology inflection point due to large-scale parallelism, including parallel operations on the contents of a single register, pipelining, memory pre-fetch, single-core simultaneous multithreading (”hyper-threading”) and superscalar instruction issue. Some new processor options have emerged, such as the Cell BE processor and GPUs, which are extremely aggressive in their use of parallelism, while keeping, on the other hand, general-purpose programmability. Other processors, like FPGAs and special purpose hardware, still based on chip parallelism, are emerging for being extremely and efficiently specialized for unique tasks.

The main objective will be to demonstrate how some of the most challenging problems in computational sciences have already been ported to modern non-conventional computing platforms, presented by speakers coming from a wide computational community (physicists, chemists, engineers, computer scientists, biologists) active in the fields of algorithm re-engineering for the new architectures.

The goal of this workshop, held at the National Center for Supercomputing Applications, University of Illinois at Urbana-Champaign, was to help computational scientists in the geosciences, computational chemistry, and astronomy and astrophysics communities take full advantage of emerging high-performance computing resources based on computational accelerators, such as clusters with GPUs and Cell processors.

Slides are now available online and cover a wide range of topics including

• GPU and Cell programming tutorials
• GPU and Cell technology
• Accelerator programming, clusters, frameworks and building blocks such as sparse matrix-vector products, tree-based algorithms and in particular accelerator integration into large-scale established code bases
• Case studies and posters from geosciences, computational chemistry and astronomy/astrophysics such as the simulation of earthquakes, molecular dynamics, solar radiation, tsunamis, weather predictions, climate modeling and n-body systems as well as Monte-Carlo, Euler, Navier-Stokes and Lattice-Boltzmann type of simulations

(National Center for Supercomputing Applications, University of Illinois at Urbana-Champaign: Path to Petascale workshop presentations, organized by Wen-mei Hwu, Volodymyr Kindratenko, Robert Wilhelmson, Todd Martínez and Robert Brunner)

During the last decade, the fundamental Satisfiability Problem (SAT) has been extensively studied. The interest of the community significantly grows because of its conceptual simplicity and its ability to describe a wide set of various problems, including hardware verification, planning, automated reasoning, and others. Consequently, there is an increasing demand for high performance SAT-solving algorithms in industry. In spite of the actual trend in processor development, which is moving from single-core to multicore CPU, there exist few parallel solving approaches dedicated to SAT problems using shared memory architectures.

This workshop will focus on SAT and beyond SAT solving techniques exploiting parallelism in emerging massively multithreaded and multicore architectures. Recently, Graphics Processing Units (GPUs) have evolved to address programming of general-purpose computations. The workshop will particularly focus on the use of GPUs and coprocessor computing techniques to overcome traditional barriers to parallelization.

The workshop invites papers in this emerging discipline which includes, but is not limited to, the following areas of interest.

• Satisfiability Solving Using Shared Memory
• General-Purpose Computation on GPUs (GPGPU) for SAT
• Reconfigurable Computing and FPGA for SAT
• Parallel SAT, MaxSAT, #SAT and QBF pre-processing

For more information visit the workshop website.

A half-day workshop and discussion forum will be held from 8:45-13:00, Wednesday May 27, in Lecture theatre 3 of the Alan Gilbert Building at The University of Melbourne, Victoria, Australia. A  light lunch will be supplied afterwards from 13:00-14:00. With speakers from NVIDIA and Xenon Systems, this workshop is hosted by the ARC Centre of Excellence for Mathematics and Statistics of Complex Systems (MASCOS), and the Department of Mathematics and Statistics at the University of Melbourne.

Due to recent advances in GPU hardware and software, so called general-purpose GPU computing (GPGPU) is rapidly expanding from niche applications to the mainstream of high performance computing. For HPC researchers, hardware gains have increased the imperative to learn this new computing paradigm, while high level programming languages (in particular, CUDA) have decreased the barrier to entry to this field, so that it is now possible for new developers to rapidly port suitable applications from C/C++ running on CPUs to CUDA running on GPUs. For appropriate applications, GPUs have significant, even dramatic, advantages compared to CPUs in terms of both Dollars/FLOPS and Watts/FLOPS.

For more information see the workshop announcement.

A GPU computing workshop and discussion forum will be held at the UWA University Club Thursday, May 7th.  The workshop aims to provide a detailed introduction to GPU computing with CUDA and NVIDIA Tesla computing solutions, and to present research in GPU and Heterogeneous computing being undertaken in Western Australia.

Mark Harris (NVIDIA) will present an introduction to the CUDA architecture, programming model, and the programming environment of C for CUDA, as well as an overview of the Tesla GPU architecture, a live programming demo, and strategies for optimizing CUDA applications for the GPU. To better enable the uptake of this technology, Dragan Dimitrovici from Xenon Systems will provide an overview of CUDA enabled hardware options. The workshop will also include brief presentations of some of the projects using CUDA within Western Australia, including a presentation from Professor Karen Haines (WASP@UWA) on parallel computing strategies required for optimizing applications for GPU and heterogeneous computing.

Please see the workshop flyer for full details.

Update: Slides from the UNSW GPU Computing Workshop are now available at the workshop website.

This half-day Workshop on High Performance GPU Computing with NVIDIA CUDA will be hosted by the Computer Science & Engineering department of the University of New South Wales, Sydney, Australia next Friday, April 17, 2009.  The workshop will provide an introduction to the CUDA architecture, programming model, and the programming environment of C for CUDA, as well as an overview of the Tesla GPU architecture, a live programming demo, and strategies for optimizing CUDA applications for the GPU. The workshop will also include a brief presentation of some of the projects using CUDA within the School of Computer Science and Engineering, UNSW, and of the hardware requirements for getting started with CUDA. The speakers are Mark Harris (NVIDIA), Manuel Chakravarty (UNSW), and Dragan Dimitrovici (Xenon Systems).  Registration is free, but mandatory, and the number of seats is limited to 50. For more information and registration details, visit the workshop webpage.

The 2009 SPEEDUP workshop will focus on Multicore computing and Parallel Languages. Topics include, but are not limited to OpenCL, NVIDIA CUDA, the Cell processor and GPU Computing. The event will take place in Lausanne, Switzerland, on September 7 and 8, 2009. The second day features a tutorial on GPU Computing with NVIDIA CUDA, organized by Dominik Göddeke (TU Dortmund), Robert Strzodka (Max Planck Institute Informatik) and Christian Sigg (NVIDIA).

The 2009 workshop on Architecture-aware Simulation and Computing, held in conjunction with the 2009 International Conference on High Performance Computing & Simulation (HPCS 2009), will include a couple of talks on GPU computing. Please see the workshop website for more information. Registration information and the full conference program will be available soon.