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	<title>GPGPU &#187; Tag: Graph Algorithms :: GPGPU.org</title>
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	<link>http://gpgpu.org</link>
	<description>General-Purpose Computation on Graphics Hardware</description>
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		<title>Scalable GPU graph traversal</title>
		<link>http://gpgpu.org/2012/04/17/scalable-gpu-graph-traversal</link>
		<comments>http://gpgpu.org/2012/04/17/scalable-gpu-graph-traversal#comments</comments>
		<pubDate>Tue, 17 Apr 2012 16:19:41 +0000</pubDate>
		<dc:creator>dom</dc:creator>
				<category><![CDATA[Research]]></category>
		<category><![CDATA[Graph Algorithms]]></category>
		<category><![CDATA[NVIDIA CUDA]]></category>
		<category><![CDATA[Papers]]></category>
		<category><![CDATA[Parallel Algorithms]]></category>

		<guid isPermaLink="false">http://gpgpu.org/?p=4634</guid>
		<description><![CDATA[Abstract: Breadth-first search (BFS) is a core primitive for graph traversal and a basis for many higher-level graph analysis algorithms. It is also representative of a class of parallel computations whose memory accesses and work distribution are both irregular and data-dependent. Recent work has demonstrated the plausibility of GPU sparse graph traversal, but has tended [...]]]></description>
			<content:encoded><![CDATA[<p>Abstract:</p>
<blockquote><p>Breadth-first search (BFS) is a core primitive for graph traversal and a basis for many higher-level graph analysis algorithms. It is also representative of a class of parallel computations whose memory accesses and work distribution are both irregular and data-dependent. Recent work has demonstrated the plausibility of GPU sparse graph traversal, but has tended to focus on asymptotically inefficient algorithms that perform poorly on graphs with non-trivial diameter.</p>
<p>We present a BFS parallelization focused on fine-grained task management constructed from efficient prefix sum that achieves an asymptotically optimal O(|V|+|E|) work complexity. Our implementation delivers excellent performance on diverse graphs, achieving traversal rates in excess of 3.3 billion and 8.3 billion traversed edges per second using single and quad-GPU configurations, respectively. This level of performance is several times faster than state-of-the-art implementations both CPU and GPU platforms.</p></blockquote>
<p>(Duane Merrill, Michael Garland and  Andrew Grimshaw: <em>&#8220;Scalable GPU graph traversal&#8221;</em>, Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP&#8217;12), pp.117-128, Feburary 2012. [<a title="DOI link to the paper" href="http://dx.doi.org/10.1145/2145816.2145832" target="_blank">DOI</a>])</p>
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		<title>A GPU-accelerated bioinformatics application for large-scale protein networks</title>
		<link>http://gpgpu.org/2011/02/10/gpu-accelerated-large-scale-protein-networks</link>
		<comments>http://gpgpu.org/2011/02/10/gpu-accelerated-large-scale-protein-networks#comments</comments>
		<pubDate>Fri, 11 Feb 2011 03:57:26 +0000</pubDate>
		<dc:creator>Mark Harris</dc:creator>
				<category><![CDATA[Research]]></category>
		<category><![CDATA[Bioinformatics]]></category>
		<category><![CDATA[Graph Algorithms]]></category>
		<category><![CDATA[High-Performance Computing]]></category>
		<category><![CDATA[NVIDIA CUDA]]></category>
		<category><![CDATA[Papers]]></category>
		<category><![CDATA[Protein Interaction Network]]></category>

		<guid isPermaLink="false">http://gpgpu.org/?p=3251</guid>
		<description><![CDATA[Abstract: Proteins, nucleic acids, and small molecules form a dense network of molecular interactions in a cell. The architecture of molecular networks can reveal important principles of cellular organization and function, similarly to the way that protein structure tells us about the function and organization of a protein. Protein complexes are groups of proteins that [...]]]></description>
			<content:encoded><![CDATA[<p>Abstract:</p>
<blockquote><p>Proteins, nucleic acids, and small molecules form a dense network of molecular interactions in a cell. The architecture of molecular networks can reveal important principles of cellular organization and function, similarly to the way that protein structure tells us about the function and organization of a protein. Protein complexes are groups of proteins that interact with each other at the same time and place, forming a single multimolecular machine. Functional modules, in contrast, consist of proteins that participate in a particular cellular process while binding each other at a different time and place.</p>
<p>A protein-protein interaction network is represented as proteins are nodes and interactions between proteins are edges. Protein complexes and functional modules can be identified as highly interconnected subgraphs and computational methods are now inevitable to detect them from protein interaction data. In addition, High-throughput screening techniques such as yeast two-hybrid screening enable identification of detailed protein-protein interactions map in multiple species. As the interaction dataset increases, the scale of interconnected protein networks increases exponentially so that the increasing complexity of network gives computational challenges to analyze the networks.<span id="more-3251"></span></p>
<p>Graphics hardware is recently widely used in high-performance computing due to its cost effectiveness. Bioinformatics applications also exploit GPU as a massive parallel multi-core processor to address computational challenges in the many areas such as sequence analysis and protein structure prediction. However, few attempts have been made to analyze biological networks.</p>
<p>We present a fast parallel implementation using commodity graphics hardware based a well-known sequential complex finding algorithm of MCODE to address the computational challenge. Our parallel algorithm is implemented on the NVIDIA parallel computing architecture of CUDA. It is evaluated for a various kinds of  large-scale PPI networks. Our GPU accelerated implementation using the latest NVIDIA graphics hardware  achieves a speedup of two orders of magnitudes compared to the original MCODE in the latest CPU for large-scale protein-protein interaction networks.</p></blockquote>
<p>(Jun Sung Yoon and Won-Hyung Jung, &#8220;A GPU-accelerated bioinformatics application for large-scale protein interaction networks&#8221;, Asia Pacific Bioinformatics Conference, 2011. [<a href="http://www.allegroviva.com/csplugins/allegromcode/APBC2011_Poster_GPU_APP_PPI.pdf" target="_blank">pdf</a>] [<a href="http://www.allegroviva.com/allegromcode" target="_blank">Project Webpage</a>])</p>
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		<title>Uncluttering Graph Layouts Using Anisotropic Diffusion and Mass Transport</title>
		<link>http://gpgpu.org/2009/11/24/uncluttering-graph-layouts</link>
		<comments>http://gpgpu.org/2009/11/24/uncluttering-graph-layouts#comments</comments>
		<pubDate>Wed, 25 Nov 2009 00:00:58 +0000</pubDate>
		<dc:creator>Mark Harris</dc:creator>
				<category><![CDATA[Research]]></category>
		<category><![CDATA[Graph Algorithms]]></category>
		<category><![CDATA[Papers]]></category>

		<guid isPermaLink="false">http://gpgpu.org/?p=1945</guid>
		<description><![CDATA[Abstract: Many graph layouts include very dense areas, making the layout difficult to understand. In this paper, we propose a technique for modifying an existing layout in order to reduce the clutter in dense areas. A physically-inspired evolution process, based on a modified heat equation is used to create an improved layout density image, making [...]]]></description>
			<content:encoded><![CDATA[<p>Abstract:</p>
<blockquote><p>Many graph layouts include very dense areas, making the layout difficult to understand. In this paper, we propose a technique for modifying an existing layout in order to reduce the clutter in dense areas. A physically-inspired evolution process, based on a modified heat equation is used to create an improved layout density image, making better use of available screen space. Using results from optimal mass transport problems, a warp to the improved density image is computed. The graph nodes are displaced according to the warp. The warp maintains the overall structure of the graph, thus limiting disturbances to the mental map, while reducing the clutter in dense areas of the layout. The complexity of the algorithm depends mainly on the resolution of the image visualizing the graph and is linear in the size of the graph. This allows scaling the computation according to required running times. It is demonstrated how the algorithm can be significantly accelerated using a graphics processing unit (GPU), resulting in the ability to handle large graphs in a matter of seconds. Results on several layout algorithms and applications are demonstrated.</p></blockquote>
<p>(Yaniv Frishman, Ayellet Tal, <a href="http://doi.ieeecomputersociety.org/10.1109/TVCG.2009.55">&#8220;Uncluttering Graph Layouts Using Anisotropic Diffusion and Mass Transport&#8221;</a>, IEEE Transactions on Visualization and Computer Graphics, vol. 15, no. 5, pp. 777-788, Sep./Oct. 2009)</p>
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		<item>
		<title>Conference Proceedings: HPG and SIGGRAPH 2009</title>
		<link>http://gpgpu.org/2009/08/23/hpg-siggraph-2009</link>
		<comments>http://gpgpu.org/2009/08/23/hpg-siggraph-2009#comments</comments>
		<pubDate>Mon, 24 Aug 2009 01:15:30 +0000</pubDate>
		<dc:creator>dom</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Research]]></category>
		<category><![CDATA[Conferences]]></category>
		<category><![CDATA[Graph Algorithms]]></category>
		<category><![CDATA[High-Performance Graphics]]></category>
		<category><![CDATA[Papers]]></category>
		<category><![CDATA[Ray Tracing]]></category>
		<category><![CDATA[SIGGRAPH]]></category>
		<category><![CDATA[stream compaction]]></category>

		<guid isPermaLink="false">http://gpgpu.org/?p=1810</guid>
		<description><![CDATA[Ke-Sen Huang has assembled a web page with links to all papers presented at these two important conferences, High Performance Graphics (a synthesis of the Graphics Hardware and Interactive Ray Tracing conferences) and SIGGRAPH. Both conferences had quite a number of GPGPU-related publications.  Highlights from HPG include a paper on computing minimum spanning trees on [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://kesen.huang.googlepages.com/" target="_blank">Ke-Sen Huang</a> has assembled a web page with links to all papers presented at these two important conferences, <a href="http://highperformancegraphics.org/" target="_blank">High Performance Graphics</a> (a synthesis of the Graphics Hardware and Interactive Ray Tracing conferences) and <a href="http://www.siggraph.org/s2009/" target="_blank">SIGGRAPH</a>. Both conferences had quite a number of GPGPU-related publications.  Highlights from HPG include a paper on computing minimum spanning trees on the GPU, one on optimizing stream compaction on GPUs, and a study from NVIDIA on understanding the efficiency of GPUs and of wide-SIMD architectures in general on inherently imbalanced workloads like ray tracing (among others).</p>
<p>Click <a href="http://kesen.huang.googlepages.com/sig2009.html" target="_blank">here for SIGGRAPH papers</a>, and <a href="http://kesen.huang.googlepages.com/hpg2009Papers.htm" target="_blank">here for HPG papers</a>. <a href="http://kesen.huang.googlepages.com/" target="_blank">Ke-Sen&#8217;s pages</a> are also a good resource for other conferences in the field.</p>
]]></content:encoded>
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		</item>
		<item>
		<title>Graph Layout on the GPU</title>
		<link>http://gpgpu.org/2008/05/25/graph-layout-on-the-gpu</link>
		<comments>http://gpgpu.org/2008/05/25/graph-layout-on-the-gpu#comments</comments>
		<pubDate>Mon, 26 May 2008 00:01:21 +0000</pubDate>
		<dc:creator>Mark Harris</dc:creator>
				<category><![CDATA[Research]]></category>
		<category><![CDATA[Graph Algorithms]]></category>
		<category><![CDATA[Papers]]></category>

		<guid isPermaLink="false">http://gpgpu.site/?p=439</guid>
		<description><![CDATA[A graph is an ordered pair G=(V,E) where V is a set of nodes and E is a set of edges connecting nodes. Graph drawing addresses the problem of creating geometric representations of graphs. Unlike matrices or images, graphs are unstructured and hence graph layout may not seem to be suitable for acceleration on the [...]]]></description>
			<content:encoded><![CDATA[<p>A graph is an ordered pair G=(V,E) where V is a set of nodes and E is a set of edges connecting nodes. Graph drawing addresses the problem of creating geometric representations of graphs. Unlike matrices or images, graphs are unstructured and hence graph layout may not seem to be suitable for acceleration on the GPU. These papers present two GPU-accelerated graph drawing algorithms which are able to quickly compute aesthetic layouts of large graphs. One is for the layout of a single graph and the other is for computing stable layouts of a sequence of graphs. Speedups of 5.5x to 17x relative to a CPU implementation are demonstrated. (Yaniv Frishman and Ayellet Tal, <a title="Link to paper" href="http://doi.ieeecomputersociety.org/10.1109/TVCG.2007.70580" target="_blank">Multi-Level Graph Layout on the GPU</a>, IEEE Transactions on Visualization and Computer Graphics (Proceedings Information Visualization 2007), 13(6):1310-1317, 2007)<br />
(Yaniv Frishman and Ayellet Tal, <a title="Link to paper" href="http://doi.ieeecomputersociety.org/10.1109/TVCG.2008.11" target="_blank"> Online Dynamic Graph Drawing</a>, accepted to IEEE Transactions on Visualization and Computer Graphics)</p>
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