The 3rd International Conference on Metaheuristics and Nature Inspired Computing, META’10, features a special session on Metaheuristics on graphics hardware, organized by Geir Hasle and Trond Runar Hagen. It focuses on the utilization of modern commodity computer architectures, in particular Graphics Processing Units (GPUs), to enhance the performance of metaheuristics. A broad spectrum of papers is invited, ranging from case studies focused on specific problems and applications to theoretical aspects and frameworks.

The conference will take place October 28-30, 2010, on Djerba Island, Tunisia. More information is available at the conference web page.

The HiBi workshop establishes a forum to link researchers in the areas of parallel computing and computational systems biology. One of the main limitations in managing models of biological systems comes from the fundamental difference between the high parallelism evident in biochemical reactions and the sequential environments employed for the analysis of these reactions. Such limitations affect all varieties of continuous, deterministic, discrete and stochastic models; undermining the applicability of simulation techniques and analysis of biological models. The goal of HiBi is therefore to bring together researchers in the fields of high performance computing and computational systems biology. Experts from around the world will present their current work, discuss
profound challenges, new ideas, results, applications and their experience relating to key aspects of high performance computing in biology.

Topics of interest include, but are not limited to:

• Parallel stochastic simulation
• Biological and Numerical parallel computing
• Parallel and distributed architectures
• Emerging processing architecture: Cell processors, GPUs, mixed CPU-FPGA, etc.
• Parallel model checking techniques
• Parallel parameter estimation
• Parallel algorithms for biological analysis
• Application of concurrency theory to biology
• Parallel visualization algorithms
• Web-services and Internet computing for e-Science
• Tools and applications

More Information: http://www.cosbi.eu/hibi2010/

High-Performance Graphics 2010 continues last year’s success at synthesizing two important and cutting-edge topics in computer graphics, the previous Graphics Hardware and Interactive Ray Tracing conferences. The scope of the conference is the overarching field of performance-oriented graphics systems, covering innovative algorithms, efficient implementations, and hardware architecture. This broader focus offers a common forum bringing together researchers, engineers, and architects to discuss the complex interactions of massively parallel hardware, novel programming models, efficient graphics algorithms, and innovative applications.

The program features three days of paper and industry presentations, with ample time for discussions during breaks, lunches, and the  conference banquet. The conference, which will take place on June 25-27, is co-located with Eurographics Rendering Symposium on the campus of the Max-Planck  Institut Informatik, Saarland University, Saarbrucken, Germany.

Original and innovative performance-oriented contributions are invited from all areas of graphics, including hardware architectures, rendering, physics, animation, AI, simulation, data structures, with topics including (but not limited to):

• New graphics hardware architectures
• Rendering architectures and algorithms
• Parallel computing for graphics (including GPU Computing)
• Algorithmic foundations
• Languages and compilation

The conference website with additional information is located at http://www.highperformancegraphics.org.

This workshop will be held in conjunction with CIT 2010, Bradford, UK, 29 June – 01 July, 2010.  From the announcement:

We are undergoing a new revolution in parallel processor technologies, especially the Graphics Processing Units. GPUs have become widely used nowadays to accelerate a broad range of applications, including computational finance, numerical computing, image/video processing, engineering simulations, quantum chemistry, just to name a few.
The goal of this workshop is to provide a forum for researchers and practitioners to discuss and share their research and development experiences and outputs on the massively parallel GPU platforms, software development tools, optimization techniques, parallel algorithm design, and all kinds of successful applications. We solicit original and previously unpublished papers addressing research challenges and advances towards the design, implementation and evaluation of massively parallel GPU computing.

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Multi- and many-core microprocessors are being deployed in a broad spectrum of applications including Clusters, Clouds and Grids. Both conventional multi- and many-core processors, such as Intel Nehalem and IBM Power7 processors, and unconventional many-core processors, such as NVIDIA Tesla and AMD FireStream GPUs, hold the promise of increasing performance through parallelism. However, GPU approaches in parallelism are distinctly different from those of conventional multi- and many-core processors, which raises new challenges: For example, how do we optimize applications for conventional multi- and many-core processors? How do we reengineer applications to take advantage of GPUs’ tremendous computing power in a reasonable cost-benefit ratio? What are effective ways of using GPUs as accelerators? The goals of this workshop are to discuss these and other issues and bring together developers of application algorithms and experts in utilizing multi- and many-core processors. Accepted papers will be published in the CCGRID proceedings. Selected papers will be published in a special issue of the Journal Concurrency and Computation: Practice and Experience.

Topics of interests include (but not limited to): Read the rest of this entry »

High throughput architectures for HPC seem likely to emphasize many cores with deep multithreading, wide SIMD, and sophisticated memory hierarchies. GPUs present one example, and their high throughput has led a number of researchers to port computationally intensive applications to NVIDIA’s CUDA architecture.

This session explored the art of performance tuning for CUDA using several case studies. Topics included profiling to identify bottlenecks, effective use of the GPU’s memory hierarchy and DRAM interface to maximize bandwidth, data versus task parallelism, and avoiding SIMD divergence.  Many of the lessons learned in the context of CUDA are likely to apply to other many-core architectures used in HPC applications.

The presentation slides from the Supercomputing 2009 full-day tutorial “High-Performance Computing with CUDA” are now available at http://gpgpu.org/sc2009.

Abstract:

NVIDIA’s CUDA is a general-purpose architecture for writing highly parallel applications. CUDA provides several key abstractions—a hierarchy of thread blocks, shared memory, and barrier synchronization—for scalable high-performance parallel computing. Scientists throughout industry and academia use CUDA to achieve dramatic speedups on production and research codes. The CUDA architecture supports many languages, programming environments, and libraries including C, Fortran, OpenCL, DirectX Compute, Python, Matlab, FFT, LAPACK, etc.

In this tutorial NVIDIA engineers will partner with academic and industrial researchers to present CUDA and discuss its advanced use for science and engineering domains. The morning session will introduce CUDA programming, motivate its use with many brief examples from different HPC domains, and discuss tools and programming environments. The afternoon will discuss advanced issues such as optimization and sophisticated algorithms/data structures, closing with real-world case studies from domain scientists using CUDA for computational biophysics, fluid dynamics, seismic imaging, and theoretical physics.

24th International Conference on Supercomputing (ICS’10)
June 1-4, 2010
Epochal Tsukuba (Tsukuba International Congress Center)
Tsukuba, Japan
Sponsored by ACM/SIGARCH

ICS is the premier international forum for the presentation of research results in high-performance computing systems.  In 2010 the conference will be held at the Epochal Tsukuba (Tsukuba International Congress Center) in Tsukuba City, the largest high-tech and academic
city in Japan.

Papers are solicited on all aspects of research, development, and application of high-performance experimental and commercial systems. Special emphasis will be given to work that leads to better understanding of the implications of the new era of million-scale parallelism and Exa-scale performance; including (but not limited to): Read the rest of this entry »

If you can’t make it to NVIDIA’s inaugural GPU Technology Conference, taking place Sept. 30 to Oct. 2, 2009 in San Jose, CA, you can watch a live webcast here.

Links for the live webcast, event coverage complete with blogs, photos and video interviews, and more details around the conference, including conference schedule, session abstracts and speaker bios can be found at www.nvidia.com/gtc.

The schedule of live webcasts is as follows:

• Wed. Sept 30 – 1:00 PM to 2:30 PM: Opening Keynote with Jen-Hsun Huang, CEO and Co-Founder, NVIDIA
• Wed. Sept 30 – 3:00 PM to 4:15 PM: General Session on Important Trends in Visual Computing
• Wed. Sept 30 – 4:30 PM to 5:45 PM: General Session on Breakthroughs in High Performance Computing
• Thurs. Oct 1 – 9:00 AM to 10:30 AM: Day 2 Keynote with Hanspeter Pfister, Professor and Computing Visionary, Harvard University
• Fri. Oct 2 – 8:30 AM to 10:00 AM: Day 3 Keynote with Richard Kerris, CTO, Lucasfilm

Ke-Sen Huang has assembled a web page with links to all papers presented at these two important conferences, High Performance Graphics (a synthesis of the Graphics Hardware and Interactive Ray Tracing conferences) and SIGGRAPH. Both conferences had quite a number of GPGPU-related publications.  Highlights from HPG include a paper on computing minimum spanning trees on the GPU, one on optimizing stream compaction on GPUs, and a study from NVIDIA on understanding the efficiency of GPUs and of wide-SIMD architectures in general on inherently imbalanced workloads like ray tracing (among others).

Click here for SIGGRAPH papers, and here for HPG papers. Ke-Sen’s pages are also a good resource for other conferences in the field.