The HiBi workshop establishes a forum to link researchers in the areas of parallel computing and computational systems biology. One of the main limitations in managing models of biological systems comes from the fundamental difference between the high parallelism evident in biochemical reactions and the sequential environments employed for the analysis of these reactions. Such limitations affect all varieties of continuous, deterministic, discrete and stochastic models; undermining the applicability of simulation techniques and analysis of biological models. The goal of HiBi is therefore to bring together researchers in the fields of high performance computing and computational systems biology. Experts from around the world will present their current work, discuss profound challenges, new ideas, results, applications and their experience relating to key aspects of high performance computing in biology.

More information and the full call can be found here: http://www.adms-conf.org/

From the call for papers:

The current data management scenario is characterized by the following trends: traditional OLTP and OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data, complex queries under real-time constraints, etc.); applications are becoming far more distributed, often consisting of different data processing components; non-traditional domains such as bio-informatics, social networking, mobile computing, sensor applications, gaming are generating growing quantities of data of different types; economical and energy constraints are leading to greater consolidation and virtualization of resources; and analyzing vast quantities of complex data is becoming more important than traditional transactional processing.

At the same time, there have been tremendous improvements in processor and memory technologies. Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple application domains. Commodity systems are increasingly using multi-core processors with more than 4 cores per chip and enterprise-class systems are using processors with at least 32 cores per chip. Specialized multi-core processors such as the Cell and many-core GPUs have brought the computational capabilities of supercomputers to cheaper commodity machines. On the storage front, FLASH-based solid state devices (SSDs) are becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like Phase-change memory are on the near-term horizon and can be game-changers in the way data is stored and processed.

In spite of the trends, currently there is limited usage of these technologies in data management domain. Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to evaluate applications in a holistic manner to ensure effective utilization of processor and memory resources. This workshop aims to understand impact of modern hardware technologies on accelerating core components of data management workloads. Specifically, the workshop hopes to explore the interplay between overall system design, core algorithms, query optimization strategies, programming approaches, performance modelling and evaluation, etc., from the perspective of data management applications.

The suggested topics of interest include, but are not restricted to:

• Hardware and System Issues in Domain-specific Accelerators
• New Programming Methodologies for Data Management Problems on Modern Hardware
• Query Processing for Hybrid Architectures
• Autonomic Tuning for Data Management Workloads on Hybrid Architectures
• Algorithms for Accelerating Multi-modal Multi-tiered Systems
• Energy Efficient Software-Hardware Co-design for Data Management Workloads
• Parallelizing non-traditional (e.g., graph mining) workloads
• Algorithms and Performance Models for modern Storage Sub-systems
• Data Layout Issues for Modern Memory and Storage Hierarchies
• New Benchmarking Methodologies for Storage-class Memories

Anchorage, home to moose, bears, birds and whales, is strategically located at almost equal flying distance from Europe, Asia and the Eastern USA. Embraced by six mountain ranges, with views of Mount McKinley in Denali National Park, and warmed by a maritime climate, the area offers year-round adventure, recreation, and sporting events. It is a fitting destination for IPDPS to mark a quarter century of tracking developments in computer science.  IPDPS serves as a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. The five-day program will follow the usual format of contributed papers, invited speakers, and panels mid week, framed by workshops held on the first and last days.  To celebrate the 25th year of IPDPS, plan to come early and stay late and also enjoy a modern city surrounded by spectacular wilderness. For updates on IPDPS 2011, visit the Web at www.ipdps.org.

GPU Developers Summit: Session Topics deadline: June 1, 2010
Emerging Companies Summit: “CEO on Stage” Nominations deadline: August 1, 2010
NVIDIA Research Summit: Posters deadline: August 15, 2010

To submit a proposal, you will be asked to set up a GTC 2010 account so you can track the status of your submission.

Submission guidelines: www.nvidia.com/object/call_for_submissions.html
Join GTC 2010 mailing list: www.nvidia.com/object/email_updates.html

Under physical constraints such as power, speed, and/or cost, the data throughput and degree of data dependence of imaging applications suggest a good match between parallel architectures and imaging applications; similarly, the choice of parallel architectures often reflects the structure of the imaging problem targeted by the application. Thus, the duality of imaging problem definition and parallelism implies that the efficient implementation of parallelism for imaging offers insight into the mind’s internal imaging computation. This duality also implies that measures of parallel efficiency can formalize the definition of many imaging problems. This conference explores this duality through new parallel designs for imaging and architectures and design tools to optimize parallelism in imaging algorithms.

Papers submitted to this conference should fuse parallel implementation design principles under physical constraints with an understanding of imaging applications; and are expected to combine principles and techniques for parallelism, such as:

• cloud computing
• GPU computing
• high-level parallel programming constructs
• design tools for extracting parallelism
• efficient, scalable architectures
• memory hierarchy design for parallel systems
• metrics for parallelism and capacity planning
• efficient algorithm mapping onto parallel hardware
• algorithmic classification by efficient parallel architecture
• algorithms for parallel scheduling and resource allocation

The full Call for Papers and detailed submission information is available at http://tinyurl.com/ei111ppia.

This workshop will be held in conjunction with Euro-Par 2010, Ischia, Naples, Italy, on August 30, 2010. More information and the full call for papers are available on the workshop homepage.

After the tremendous success of the first seven entries to the ShaderX book series, and the upcoming success of the GPU Pro book, we are looking for authors for GPU Pro 2. The upcoming book will cover advanced rendering techniques that run on the DirectX and/or OpenGL run-time or any other run-time with any language available. It will include topics on: Geometry Manipulation; Rendering Techniques; Handheld Devices Programming; Effects in Image Space; Shadows; 3D Engine Design; Graphics Related Tools; Environmental Effects and a dedicated section on mathematics used in graphics programming.

Proposals are due by May 17th, 2010. Please send them to wolf at shaderx.com. An example proposal, writing guidelines and a FAQ can be downloaded from http://gpupro2.blogspot.com/.

As with the first volume, the theme of the book includes everything having to do with game engine design and implementation. Specific topics of interest include rendering techniques, shaders, OpenGL / DirectX, physics / collision detection, mathematics, programming techniques, engine architecture, visibility determination, audio, user interface, input devices, memory management, artificial intelligence, resource organization, and cross-platform considerations. This list is not exhaustive, and the editors are happy to evaluate any idea that pertains to making game engines.

• Innovative use of hardware and software unconventional for HPC
• HPC applications or visualizations in connection with HPC on GPUs (GPGPU), IBM Cell, Low Power Processors, FPGAs, Visualization cards etc.
• Cluster/Grid solutions using unconventional hardware, e.g. clusters of PS3s, GPUs, Low Power Processors, FPGAs etc.
• Performance and scalability studies in HPC using unconventional hardware
• Reconfigurable Computing for HPC
• Performance modeling, analysis and tools for HPC with unconventional hardware
• New or adapted/extended (parallel) programming models for HPC with unconventional hardware

The submission deadline is June 14th, and the full call for papers along with further information and submission instructions can be found at http://uchpc10.cs.tum.edu.

The conference will take place October 28-30, 2010, on Djerba Island, Tunisia. More information is available at the conference web page.