High Throughput Parallel Molecular Dynamics for GPUs

April 6th, 2011

The North Carolina Renaissance Computing Institute (RENCI) is running Amber PMEMD on the Open Science Grid, the high throughput computing (HTC) fabric used by the Large Hadron Collider (LHC). This approach is likely to be helpful to researchers with any of these challenges:

  1. Constrained by limited computing resources including access to GPGPUs
  2. Manually executing the same simulation repeatedly with different parameters
  3. Making simulations easier to understand, share, scale and re-use across compute resources

For more information see these two blog posts: High Throughput Parallel Molecular Dynamics and CUDA/Tesla Accelerated PMEMD on OSG. Contact Steve Cox (scox@renci.org) if you’d like to discuss further and determine if your application is a fit. If it is, RENCI can provide access to the grid as well as tools for executing and managing simulations.

CIGPU 2011 Submission deadline 7 April 2011

April 6th, 2011

The fourth International workshop and tutorial on Computational Intelligence on Consumer Games and Graphics Hardware (CIGPU 2011) will be held in Dublin 13 July 2011. Submissions are invited in (but not limited to): Parallel genetic algorithms, GP, EP, ES, PSO, ACO, DE, Computational Biology, EC on video game platforms and mobile devices. Papers that discuss novel implementations and the practicalities of writing software for these hardware platforms are especially welcome.

Papers should be submitted by 7 April, 2011 in PDF format via email to: cigpu@gpgpgpu.com and contain the subject “GECCO Workshop”

Real-space calculation of powder diffraction patterns on graphics processing units.

March 29th, 2011

Abstract:

Diffraction, particularly of X-rays, is a powerful technique for the investigation of structure, microstructure and dynamical properties of matter. In order to link theoretical methods, like Molecular Dynamics and other atomistic approaches, and diffraction experiments we developed a new software for calculating the powder diffraction pattern of nano-sized objects on the GPUs. The software, soon to be made available under GPL license, allows the use of GPUs on different hosts for a direct (brute-force) computation of the Debye scattering equation.

(L Geliso, C. L. Azanza Ricardo, M. Leoni and P. Scardi: “Real-space calculation of powder diffraction patterns on graphics processing units”, Journal of Applied Crystallography 43:647-653, 2010. [DOI])

GID2011 Deadline Extension

March 29th, 2011

The deadline for submissions to “GPU’s in Databases” GID2011 workshop has been extended to April 12th, 2011. The “GPUs in Databases” workshop is devoted to sharing the knowledge related to applying GPUs in database environments and to discuss possible future development of this application domain. The workshop topics include, but are not limited to: Read the rest of this entry »

Processing data streams with hard real-time constraints on heterogeneous systems

March 29th, 2011

Abstract:

Data stream processing applications such as stock exchange data analysis, VoIP streaming, and sensor data processing pose two conflicting challenges: short per-stream latency — to satisfy the milliseconds-long, hard real-time constraints of each stream, and high throughput — to enable efficient processing of as many streams as possible. High-throughput programmable accelerators such as modern GPUs hold high potential to speed up the computations. However, their use for hard real-time stream processing is complicated by slow communications with CPUs, variable throughput changing non-linearly with the input size, and weak consistency of their local memory with respect to CPU accesses. Furthermore, their coarse grain hardware scheduler renders them unsuitable for unbalanced multi-stream workloads.

We present a general, efficient and practical algorithm for hard real-time stream scheduling in heterogeneous systems. The algorithm assigns incoming streams of different rates and deadlines to CPUs and accelerators. By employing novel stream schedulability criteria for accelerators, the algorithm finds the assignment which simultaneously satisfies the aggregate throughput requirements of all the streams and the deadline constraint of each stream alone.

Using the AES-CBC encryption kernel, we experimented extensively on thousands of streams with realistic rate and deadline distributions. Our framework outperformed the alternative methods by allowing 50% more streams to be processed with provably deadline-compliant execution even for deadlines as short as tens milliseconds. Overall, the combined GPU-CPU execution allows for up to 4-fold throughput increase over highly-optimized multi-threaded CPU-only implementations.

( Uri Verner, Assaf Schuster and Mark Silberstein, “Processing data streams with hard real-time constraints on heterogeneous systems”, ICS’11, to appear)

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CfP: UCHPC 2011

March 29th, 2011

The 4th workshop on UnConventional High Performance Computing 2011 (UCHPC 2011), August 29th, 2011, Bordeaux, France, will be held in conjunction with Euro-Par 2011.  This workshop is organized by Anders Hast, Josef Weidendorfer and Jan-Philipp Weiss.

As the word “UnConventional” in the title suggests, the workshop focuses on hardware or platforms used for HPC, which were not intended for HPC in the first place. Reasons could be raw computing power, good performance per watt, or low cost in general. Thus, UCHPC tries to capture solutions for HPC which are unconventional today but perhaps conventional tomorrow. For example, the computing power of platforms for games recently raised rapidly. This motivated the use of GPUs for computing (GPGPU), or even building computational grids from game consoles. The recent trend of integrating GPUs on processor chips seem to be very beneficial for use of both parts for HPC. Other examples for “unconventional” hardware are embedded, low-power processors, upcoming many-core architectures, FPGAs or DSPs. Thus, interesting devices for research in unconventional HPC are not only standard server or desktop systems, but also relative cheap devices due to being mass market products, such as smartphones, netbooks, tablets and small NAS servers. For example, smartphones seem to become more performance hungry every day. Only imagination sets the limit for use.

The full call for papers including detailed submission instructions is available at http://www.lrr.in.tum.de/~weidendo/uchpc11.

CfP: High Performance Graphics 2011

March 29th, 2011

We are pleased to announce High-Performance Graphics 2011. High Performance Graphics is the leading international forum for performance-oriented graphics systems research including innovative algorithms, efficient implementations, and hardware architecture. The conference brings together researchers, engineers, and architects to discuss the complex interactions of massively parallel hardware, novel programming models, efficient graphics algorithms, and innovative applications.

The conference is co-located with ACM SIGGRAPH 2011 (Aug. 5-7) in Vancouver, Canada.  More information including the full call for papers with deadlines and submission instructions, is available at http://www.highperformancegraphics.org.

Accelerating Power Flow studies on Graphics Processing Unit

March 29th, 2011

Abstract:

In this paper, we present the design of Power Flow algorithm that has enhanced performance on the Graphics Processing Unit (GPU) using Compute Unified Device Architecture (CUDA). This work investigates the performance of optimized CPU versions of Newton-Raphson (Polar form) and Gauss-Jacobi power flow algorithms, highlights the approach used to reduce the computation time by performing these studies on massively parallel GPU cores. Simulations results demonstrate the significant acceleration of the GPU version compared to its CPU variant, thus reducing processing time making them suitable for real-time online dispatching purposes.

(Singh, J. and Aruni, I.: “Accelerating Power Flow studies on Graphics Processing Unit”, Proceedings of the Annual IEEE India Conference 2010 (INDICON), pp 1-5, Dec. 2010. [DOI])

AMD Fusion Developer Summit

March 29th, 2011

Heterogeneous computing is moving into the mainstream, and a broader range of applications are already on the way. As the provider of world-class CPUs, GPUs, and APUs, AMD offers unique insight into these technologies and how they interoperate. We’ve been working with industry and academia partners to help advance real-world use of these technologies, and to understand the opportunities that lie ahead. It’s time to share what we’ve learned so far.

With tutorials, hands-on labs, and sessions that span a range of topics from HPC to multimedia, you’ll have the opportunity to expand your view of what heterogeneous computing currently offers and where it is going. You’ll hear from industry innovators and academic pioneers who are exploring different ways of approaching problems, and utilizing new paradigms in computing to help identify solutions. You’ll meet AMD experts with deep knowledge of hardware architectures and the software techniques that best leverage those platforms. And you’ll connect with other software professionals who share your passion for the future of technology.

Learn more at developer.amd.com/afds.

CFP: First International Workshop on Accelerator Architectures for the Masses (WACy 2011)

March 29th, 2011

The First International Workshop on Accelerators Architectures for the Masses (WACy 2011) will be held in conjunction with 25th Int’l. Conference on Supercomputing (ICS 2011), on June 4th 2011. The submission of short papers (approximately ~6 pages) is encouraged. This workshop is organized by Arrvindh Shriraman and Tor Aamodt, the submission deadline is April 15th 11:59pm PST. More information is available at http://wacy.cs.sfu.ca.

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