GE has introduced three new rugged computing products featuring integrated GPGPU technology using NVIDIA CUDA-capable GPUs.  The first is the IPN250 Rugged 6U OpenVPX Single Board Computer (SBC).  The second is the 6U OpenVPX NPN240 multi-processor. The NPN240 features two NVIDIA® CUDA-capable GT240 96-core GPUs, enabling it to deliver up to 750 GFLOP/S peak per card slot (depending on the application). Multiple NPN240s can be linked to one or more hosts to create multi-node CUDA GPU clusters capable of thousands of GFLOP/S.  The third is the OpenVPX-compatible GRA111 high performance graphics board, which is the first rugged implementation of a CUDA-capable GPU.

GPU Systems has added an OpenCL back end implementation to its Libra Technology compiler and runtime architecture. Libra version 1.2 now supports x86/x64, OpenGL/OpenCL and CUDA compute back ends. The OpenCL back end generates dynamic code specifically for AMD GPUs. Also, the CUDA back end generator has been enhanced with Fermi capabilities and this new release brings full BLAS 1,2,3 matrix, vector, dense, sparse, complex, single/double standard math library functionality and access through a standard C programming interface & library. The high-level approach of the Libra API enables developers to easily extend existing high-level functionality from their favorite programming language.

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CAPS has recently added an OpenCL code generator to the just released 2.3 version of its HMPP directive-based hybrid compiler. Also, the CUDA back-end generator has been enhanced with Fermi capabilities and this new release brings support for more native compilers with Intel ifort/icc, GNU gcc/gfortran and PGI pgcc/pgfort compilers, enabling developers to freely use their favorite compiler with HMPP 2.3.

Based on GPU programming and tuning directives, HMPP offers an incremental programming model that allows developers with different levels of expertise to fully exploit GPU hardware accelerators in their legacy code. Read the rest of this entry »

nexiwave.com, a Speech Indexing Cloud Service company based in Boston MA, announces that it has completed the GPU-acceleration of its speech indexing service, Nexiwave 2.0. Without sacrificing accuracy of its service, nexiwave enjoys over 75% relative speed improvement (comparing a stock Sphinx4 running on a 2.5Ghz/8 core/24GB RAM server to a Sphinx4 on 2.5Ghz/Quad Core/4GB with NVIDIA GTX 470 GPU). Read the rest of this entry »

Jaideep Singh and Ipseeta Aruni present a GPGPU wrapper for the R statistical computing environment at the R user conference 2010. Their approach is to overload datatypes using R’s simplified wrapper and the SWIG Interface Generator functionality. A full page summary of the approach is available at the conference web site (PDF link).

Mellanox and NVIDIA have teamed up to create a solution that enables data sharing (without expensive memory copies) between CUDA-managed host memory and Mellanox Infiniband cards. NVIDIA GPUDirect technology allows application and middleware developers to improve performance by up to 30%, by providing a shared, RDMA-accessible address space between the GPU and the interconnect.

The full press release is available here.

At ISC’10, Intel demonstrated their co-processor approach to HPC (formerly known as Larrabee, now codenamed Knights Corner). A prototype of the Intel Many Integrated Core (MIC) architecture with 32 in-order cores, each equipped with a 512-wide vector unit and connected via an on-chip coherent cache, delivered more than half a Teraflop performance for LU decomposition in a live demonstration during a keynote by Kirk Skaugen.

The full press release from ISC’10 is available here.

The Australia GPU Users groups are informal special interest groups founded to bring together GPU users from all fields and experience levels to learn and share their ideas and creations at friendly meetings.  There are currently GPU users groups forming in Brisbane, Sydney, and Perth.

The groups will discuss general GPU computing, including GPGPU, CUDA, OpenCL, DirectCompute, DirectX and OpenGL and related technologies. There will be short presentations during the meetings, as well as informal discussions on a range of subjects, including core fundamentals, hardware architectures, parallel programming as well as specific optimisations and also examples of applications from different fields of industry, science and multimedia.

Sign up today: the meetings will allow you to meet others who share your interest in GPUs.

GPGPU.org is maintaining a list of GPU Users groups.  If you have a local GPU users group, please tell us about it!

At the ISC 2010 conference in Hamburg, Germany, this week, NVIDIA announced new programs for the growing CUDA/GPGPU developer community:

• CUDA Certification Program – Driven by demand for qualified GPGPU engineers, this is the first program to certify expertise in massively parallel programming on GPUs.
• CUDA Research Centers – Recognizes institutions that embrace GPU Computing across multiple research fields.
• CUDA Teaching Centers – Recognizes institutions that have integrated GPU Computing techniques into their mainstream computer programming curriculum.

These programs complement the existing CUDA Center of Excellence program, which has recognized 10 premier institutions around the world. More details are available here: http://www.nvidia.com/object/io_1275409333119.html

From a white paper by GE Intelligent Platforms (Link):

This white paper describes how GPGPU technology can allow system designers to fit an unprecedented amount of processing power into a very compact package. For example, it describes four GE Intelligent Platforms 3U VPX boards with a floating point performance of 766 GFLOPS in less than 0.4 cubic feet. With configuration control and lifecycle management from a leading COTS supplier, these technologies are clearly ready for duty.