At ISC’10, Intel demonstrated their co-processor approach to HPC (formerly known as Larrabee, now codenamed Knights Corner). A prototype of the Intel Many Integrated Core (MIC) architecture with 32 in-order cores, each equipped with a 512-wide vector unit and connected via an on-chip coherent cache, delivered more than half a Teraflop performance for LU decomposition in a live demonstration during a keynote by Kirk Skaugen.
The full press release from ISC’10 is available here.
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Will it be a discrete PCI-e accelerator like Larrabee or a regular CPU product sitting in a CPU socket on a motherboard and running the system OS? Does anybody know just what exactly was demonstrated at ISC?
At ISC, they presented a discrete PCIe device, and talked about “its own 1–2 GB of memory”. The press release links to a video it I’m not fully mistaken..
where can I get one?