Imaging translates information into and out of the visual system with today’s computation engine of choice: digital electronic systems. While scalar architectures are no longer scaling at historical rates, we see a massive explosion in the total number of connected computation devices and the ways that hardware architectures and software parallel programming environments use these devices to work in concert and in parallel. From the computing cloud to map-reduce programming models and systems to multi-core CPUs to the regular layout of graphics processing units (GPUs) to the increasing capacity of FPGA fabrics, a range of parallel architectures and parallel programming environments are available to designers and researchers to solve computationally complex problems in efficient (and often real-time) imaging applications.

Under physical constraints such as power, speed, and/or cost, the data throughput and degree of data dependence of imaging applications suggest a good match between parallel architectures and imaging applications; similarly, the choice of parallel architectures often reflects the structure of the imaging problem targeted by the application. Thus, the duality of imaging problem definition and parallelism implies that the efficient implementation of parallelism for imaging offers insight into the mind’s internal imaging computation. This duality also implies that measures of parallel efficiency can formalize the definition of many imaging problems. This conference explores this duality through new parallel designs for imaging and architectures and design tools to optimize parallelism in imaging algorithms.

Papers submitted to this conference should fuse parallel implementation design principles under physical constraints with an understanding of imaging applications; and are expected to combine principles and techniques for parallelism, such as:

• cloud computing
• GPU computing
• high-level parallel programming constructs
• design tools for extracting parallelism
• efficient, scalable architectures
• memory hierarchy design for parallel systems
• metrics for parallelism and capacity planning
• efficient algorithm mapping onto parallel hardware
• algorithmic classification by efficient parallel architecture
• algorithms for parallel scheduling and resource allocation

The full Call for Papers and detailed submission information is available at http://tinyurl.com/ei111ppia.