This ISVC 2005 paper by Ugo Erra presents parallel fractal image compression using programmable graphics hardware. The main problem of fractal compression is the very high computing time needed to encode images. The implementation in this paper exploits the SIMD architecture and inherent parallelism of recent GPUs to speed up the baseline approach of fractal encoding. The results presented are achieved on inexpensive and widely available graphics boards. (Toward Real-Time Fractal Image Compression Using Graphics Hardware. Ugo Erra. In Proceedings of International Symposium on Visual Computing 2005)